1. Field of the Invention
The present invention relates to an impedance adjustment circuit for adjusting the impedance of an input and/or output buffer circuit, and to an integrated circuit device provided with the impedance adjustment circuit.
2. Description of the Related Art
In an interface that operates at high speed, the transmission lines between a transmitting circuit, receiving circuit, and LSI (Large Scale Integrated circuit) are handled as distributed constant circuits, and impedance matching is essential. If the impedance of the transmission lines and the impedance of the load circuit do not match, reflected wave is created at the boundary between the transmission lines and the load circuit, and the reflected wave causes the input buffer circuit to malfunction. A resistance is conventionally added to the output buffer circuit in order to match the impedance. This resistance is integrated into the LSI or is mounted outside of the LSI.
In the resistance that is added to such an output buffer circuit, it is necessary to increase the ratio of the resistance value of a resistance element that is resilient against the effects of process variability and temperature variability in the entire resistance value. In the case that the resistance is composed of a MOS (Metal Oxide Semiconductor) transistor, for example, the size of the MOS transistor must be increased. However, this makes it more difficult to accommodate the transistor in the LSI area and causes the through-current, noise, and power consumption to increase.
Techniques that provide an impedance adjustment circuit inside the LSI have been developed in order to solve such problems and to improve the impedance adjustment precision (see Japanese Laid-Open Patent Application No. 2005-026890). A principal example of the adjustment method is to adjust the impedance in conjunction with the use of a high precision external resistance element. By providing an impedance adjustment circuit, the size of the MOS transistor does not need to be increased, the accommodation factor is improved, the noise and power consumption can be reduced, and an interface that operates at higher speed can be assured.
However, the prior art has the following drawbacks. In recent years, there has been a demand for an impedance adjustment circuit with higher precision due to the fact that interfaces are operating at higher speeds. It is for this reason that there is a need to improve the detection accuracy of the electric potential level when impedance has been converted to electric potential. When the power supply voltage is 1 V, for example, electric potential differences of several millivolts must be detected. With current technology, however, device variability within the chip is becoming more noticeable due to smaller integrated circuits, and there is a new need to consider the variability when circuits are designed. The Pelgrom model and other models are known as local variability models. Due to such variability, differential circuits that detect an electric potential difference of several millivolts are increasingly no longer able to be fabricated by the same convention circuit methods, and it has become difficult to achieve the required impedance adjustment precision.